* FT pin for user-configurable flow through or pipelined operation
* Single Cycle Deselect (SCD) Operation
* IEEE 1149.1 JTAG-compatible Boundary Scan
* O.

* 100-lead TQFP package -11 -11.5 -100 -80 -66 10 ns 10 ns 12.5 ns 15 ns Pipeline tCycle 10 ns 4.0 ns 4.0 ns 4.0 ns .

Applications The GS88118//36T is a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds appli.

GS88118A

GS88118B

GS88132A

GS88132B

GS88136A

GS88136B

GS88136T

GS881E18AD

GS881E18CD-xxxIV

GS881E18CGD-xxxIV

GS881E18CGT-xxxIV

GS881E18CT-xxxIV

GS881E32AD