GS8161E32DD Datasheet | GSI Technology

Features - FT pin for user-configurable flow through or pipeline operation - Dual Cycle Deselect (DCD) operation - IEEE 1149.1 JTAG-patible Boundary Scan - 2.5 V or 3.3 V +10%/- 10% core power supply - 2.5 V or 3.3 V I/O supply - LBO pin for Linear or Interleaved Burst mode - Internal input resistors on mode pins allow floating mode pins - Default to Interleaved Pipeline mode - Byte Write (BW) and/or Global Write (GW) operation - Internal self-timed write cycle - Automatic power-down for portable applications - JEDEC-standard 165-bump BGA package - Ro HS-pliant 100-pin TQFP and 165-bump BGA available Functional Description Applications The GS8161E18D(GT/D)/GS8161E32D(D)/GS8161D36D(GT/D) is an 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controls Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positiveedge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in...