GS82582T38GE
Features
- 2.5 Clock Latency
- Simultaneous Read and Write Sigma DDRTM Interface
- JEDEC-standard pinout and package
- Double Data Rate interface
- Byte Write controls sampled at data-in time
- Burst of 2 Read and Write
- On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs
- 1.8 V +100/- 100 m V core power supply
- 1.5 V or 1.8 V HSTL Interface
- Pipelined read operation
- Fully coherent read and write pipelines
- ZQ pin for programmable output drive strength
- Data Valid Pin (QVLD) Support
- IEEE 1149.1 JTAG-pliant Boundary Scan
- Ro HS-pliant 165-bump BGA package
Sigma DDR-II™ Family Overview
The GS82582T20/38GE are built in pliance with the Sigma DDR-II+ SRAM pinout standard for mon I/O synchronous SRAMs. They are 301,989,888-bit (288Mb) SRAMs. The GS82582T20/38GE Sigma DDR-II+ SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking...
