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GS82582T38GE - 288Mb SigmaDDR-II+ SRAM

Download the GS82582T38GE datasheet PDF. This datasheet also covers the GS82582T20GE variant, as both devices belong to the same 288mb sigmaddr-ii+ sram family and are provided as variant models within a single manufacturer datasheet.

Description

Table Symbol Description Type Comments SA Synchronous Address Inputs Input R/W Synchro

Features

  • 2.5 Clock Latency.
  • Simultaneous Read and Write SigmaDDRTM Interface.
  • JEDEC-standard pinout and package.
  • Double Data Rate interface.
  • Byte Write controls sampled at data-in time.
  • Burst of 2 Read and Write.
  • On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs.
  • 1.8 V +100/.
  • 100 mV core power supply.
  • 1.5 V or 1.8 V HSTL Interface.
  • Pipelined read operation.
  • Fully coheren.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GS82582T20GE-GSITechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number GS82582T38GE
Manufacturer GSI Technology
File Size 312.81 KB
Description 288Mb SigmaDDR-II+ SRAM
Datasheet download datasheet GS82582T38GE Datasheet

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Other Datasheets by GSI Technology

Part Number Description
GS82582T37GE 288Mb SigmaDDR-II+ SRAM
GS82582T19GE 288Mb SigmaDDR-II+ SRAM
GS82582T20GE 288Mb SigmaDDR-II+ SRAM
GS82582TT19GE 288Mb SigmaDDR-II+ SRAM
GS82582TT20GE 288Mb SigmaDDR-II+ SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
GS82582T20/38GE-550/500/450/400 165-Bump BGA Commercial Temp Industrial Temp 288Mb SigmaDDR-II+TM Burst of 2 SRAM 550 MHz–400 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features • 2.5 Clock Latency • Simultaneous Read and Write SigmaDDRTM Interface • JEDEC-standard pinout and package • Double Data Rate interface • Byte Write controls sampled at data-in time • Burst of 2 Read and Write • On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • Data Valid Pin (QVLD) Support • IEEE 1149.
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