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GS832136E-V Datasheet Preview

GS832136E-V Datasheet

36Mb Sync Burst SRAMs

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GS832118/32/36E-xxxV
Commercial Temp
Industrial Temp
2M x 18, 1M x 32, 1M x 36
36Mb Sync Burst SRAMs
1.8 V or 2.5 V VDD
1.8 V or 2.5 V I/O
Features
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 165-bump FP-BGA package
• RoHS-compliant 165-bump BGA package available
Functional Description
Applications
The GS832118/32/36E-xxxV is a 37,748,736-bit high
performance synchronous SRAM with a 2-bit burst address
counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPUs, the
device now finds application in synchronous SRAM
applications, ranging from DSP main store to networking chip
set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx,
BW, GW) are synchronous and are controlled by a positive-
edge-triggered clock input (CK). Output enable (G) and power
down control (ZZ) are asynchronous inputs. Burst cycles can
be initiated with either ADSP or ADSC inputs. In Burst mode,
subsequent burst addresses are generated internally and are
controlled by ADV. The burst address counter may be
configured to count in either linear or interleave order with the
Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
SCD Pipelined Reads
The GS832118/32/36E-xxxV is a SCD (Single Cycle Deselect)
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs
begin turning off their outputs immediately after the deselect
command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS832118/32/36E-xxxV operates on a 1.8 V or 2.5 V
power supply. All inputs are 1.8 V or 2.5 V compatible.
Separate output power (VDDQ) pins are used to decouple
output noise from the internal circuits and are 1.8 V or 2.5 V
compatible.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
Pipeline
tKQ
tCycle
3.0 3.0 3.0 3.5 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.6 7.5 ns
3-1-1-1 Curr (x18) 285 265 245 220 210 185 mA
Curr (x32/x36) 350 320 295 260 240 215 mA
Flow
Through
2-1-1-1
tKQ
tCycle
Curr (x18)
6.5 7.0 7.5 8.0 8.5 8.5 ns
6.5 7.0 7.5 8.0 8.5 8.5 ns
205 195 185 175 165 155 mA
Curr (x32/x36) 235 225 210 200 190 175 mA
Rev: 1.04 6/2006
1/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology




GSI Technology

GS832136E-V Datasheet Preview

GS832136E-V Datasheet

36Mb Sync Burst SRAMs

No Preview Available !

GS832118/32/36E-xxxV
165 Bump BGA—x18 Commom I/O—Top View (Package E)
1 2 3 4 5 6 7 8 9 10 11
A NC A E1 BB NC E3 BW ADSC ADV A A
A
B NC A E2 NC BA CK GW G ADSP A NC B
C NC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPA C
D
NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA
D
E
NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA
E
F
NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA
F
G
NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA
G
H FT MCL NC VDD VSS VSS VSS VDD NC NC ZZ H
J DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC
J
K DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC
K
L DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC
L
M DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC
M
N
DQPB NC VDDQ VSS
NC
A
NC VSS VDDQ NC NC
N
P
NC NC
A
A TDI A1 TDO A
A
A
A
P
R
LBO A19
A
A TMS A0 TCK A
A
A
A
R
11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch
Rev: 1.04 6/2006
2/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology


Part Number GS832136E-V
Description 36Mb Sync Burst SRAMs
Maker GSI Technology
Total Page 30 Pages
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