GS8321E18E-V Overview
Applications The GS8321E18/32/36E-xxxV is a 37,748,736-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Leve.
GS8321E18E-V Key Features
- FT pin for user-configurable flow through or pipeline operation
- Dual Cycle Deselect (DCD) operation
- IEEE 1149.1 JTAG-patible Boundary Scan
- 1.8 V or 2.5 V core power supply
- 1.8 V or 2.5 V I/O supply
- LBO pin for Linear or Interleaved Burst mode
- Internal input resistors on mode pins allow floating mode pins
- Default to Interleaved Pipeline mode
- Byte Write (BW) and/or Global Write (GW) operation
- Internal self-timed write cycle