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HDMP-0422 - Single Port Bypass Circuit

Download the HDMP-0422 datasheet PDF. This datasheet also covers the HDMP-0422_Hewlett variant, as both devices belong to the same single port bypass circuit family and are provided as variant models within a single manufacturer datasheet.

Description

The HDMP-0422 is a Single Port Bypass Circuit (PBC) with Clock and Data Recovery (CDR) capability included.

This integrated circuit provides a low-cost, lowpower physical-layer solution for Fibre Channel Arbitrated Loop (FC-AL) disk array configurations.

Features

  • Supports 1.0625 GBd Fibre Channel operation.
  • Supports 1.25 GBd Gigabit Ethernet (GE) operation.
  • Single PBC/CDR in one package.
  • CDR location determined by choice of cable input/output.
  • Amplitude valid and data valid detection (Fibre channel rate only) on FM_NODE[0] input.
  • Equalizers on all inputs.
  • High-speed LVPECL I/O.
  • Buffered Line Logic (BLL) outputs (no external bias resistors required).
  • 0.46 W typical power at.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HDMP-0422_Hewlett-Packard.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number HDMP-0422
Manufacturer Hewlett-Packard
File Size 257.00 KB
Description Single Port Bypass Circuit
Datasheet download datasheet HDMP-0422 Datasheet

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Other Datasheets by Hewlett-Packard

Part Number Description
HDMP-0421 Port Bypass Circuits
HDMP-0440 Quad Port Bypass Circuit
HDMP-0450 Quad Port Bypass Circuit
HDMP-0452 Quad Port Bypass Circuit
HDMP-0480 Octal Cell Port Bypass Circuit without Clock and Data Recovery

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com Agilent HDMP-0422 Single Port Bypass Circuit with CDR & Data Valid Detection Capability for Fibre Channel Arbitrated Loops Data Sheet Features • Supports 1.0625 GBd Fibre Channel operation • Supports 1.25 GBd Gigabit Ethernet (GE) operation • Single PBC/CDR in one package • CDR location determined by choice of cable input/output • Amplitude valid and data valid detection (Fibre channel rate only) on FM_NODE[0] input • Equalizers on all inputs • High-speed LVPECL I/O • Buffered Line Logic (BLL) outputs (no external bias resistors required) • 0.46 W typical power at VCC = 3.
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