dual j-k flip-flops (with clear).
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* High Speed Operation: tpd (Clock to Q or Q) = 14 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: V.
The flip-flop has independent data, preset, clear, and clock inputs and Q and Q outputs. The logic level present at thte data input is transferred to the output during the positive going transition to the clock pulse. Preset and clear are independent.
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