HD74HCT137 latch equivalent, 3-to-8-line decoder/demultiplexer with address latch.
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* LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed Operation: tpd (A, B, C to Y) = 18 ns typ (C L .
in bus oriented systems.
Features
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* LSTTL Output Logic Level Compatibility as well as.
The HD74HCT137 implements a three-to-eight line decoder with latches on the three address inputs. When GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as GL remains high no address cha.
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