HD74HCT126
Description
The HD74HCT125, HD74HCT126 require the 3-state control input C to be taken high to put the output into the high impedance condition, whereas the HD74HCT125, HD74HCT126 requires the control input to be low to put the output into high impedance.
Features
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- - LSTTL Output Logic Level patibility as well as CMOS Output patibility High Speed Operation: tpd (A to Y) = 12 ns typ (CL = 50 p F) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
Input C HCT125 H L L HCT126 L H H A X L H Output Y HD74HCT125 Z L H HD74HCT126 Z L H
Notes: X: Irrelevant Z: Off (High-impedance) state of a 3-state output.
HD74HCT125/HD74HCT126
Pin Arrangement
HD74HCT125
1C 1A 1Y 2C 2A 2Y GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC 4C 4A 4Y 3C 3A 3Y
(Top view)
1C 1A 1Y 2C 2A 2Y GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC 4C 4A 4Y 3C 3A...
