HD74HCT126 outputs) equivalent, quad. bus buffer gates (with 3-state outputs).
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* LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed Operation: tpd (A to Y) = 12 ns typ (CL = 50 pF.
The HD74HCT125, HD74HCT126 require the 3-state control input C to be taken high to put the output into the high impedance condition, whereas the HD74HCT125, HD74HCT126 requires the control input to be low to put the output into high impedance.
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