HD74HCT137 Datasheet - Hitachi Semiconductor

HD74HCT137 3-to-8-line Decoder/Demultiplexer with Address Latch

The HD74HCT137 implements a three-to-eight line decoder with latches on the three address inputs. When GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as GL remains high no address changes will be recognized. Output enable controls, G.

HD74HCT137 Features

* LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed Operation: tpd (A, B, C to Y) = 18 ns typ (C L = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Inpu

HD74HCT137 Datasheet (56.20 KB)

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Datasheet Details

Part number:

HD74HCT137

Manufacturer:

Hitachi Semiconductor

File Size:

56.20 KB

Description:

3-to-8-line decoder/demultiplexer with address latch.

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HD74HCT137 3-to-8-line Decoder Demultiplexer with Address Latch Hitachi Semiconductor

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