HY5MS7B2BLFP Key Features
- Mobile DDR SDRAM
- Double data rate architecture: two data transfer per clock cycle
- Mobile DDR SDRAM INTERFACE
- x32 bus width: HY5MS7B2BLFP
- MODE RERISTER SET, EXTENDED MODE REGISTER SET and STATUS REGISTER READ
- Keep to the JEDEC Standard regulation (Low Power DDR SDRAM)
- CAS LATENCY
- Programmable CAS latency 2 or 3 supported
- BURST LENGTH
- Multiplexed Address (Row address and Column address)