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HY57V28420BT - 4Banks x 8M x 4bits Synchronous DRAM

General Description

The Hynix HY57V28420B(L)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth.

HY57V28420B(L)T is organized as 4banks of 8,388,608x4.

Key Features

  • Single 3.3±0.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by DQM Internal four banks operation.
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  • Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full Page for Sequenti.

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Datasheet Details

Part number HY57V28420BT
Manufacturer SK Hynix
File Size 279.68 KB
Description 4Banks x 8M x 4bits Synchronous DRAM
Datasheet download datasheet HY57V28420BT Datasheet

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HY57V28420B(L)T 4Banks x 8M x 4bits Synchronous DRAM DESCRIPTION Preliminary The Hynix HY57V28420B(L)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V28420B(L)T is organized as 4banks of 8,388,608x4. HY57V28420B(L)T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.