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HY5DU281622FTP - 128Mb DDR SDRAM

General Description

and is subject to change without notice.

Hynix Semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Key Features

  • VDD, VDDQ = 2.3V min ~ 2.7V max (Typical 2.5V Operation +/- 0.2V for DDR266, 333) VDD, VDDQ = 2.4V min ~ 2.7V max (Typical 2.6V Operation +0.1/- 0.2V for DDR400 and 400Mbps/pin product) All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data.

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Full PDF Text Transcription (Reference)

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128Mb DDR SDRAM HY5DU281622FTP www.DataSheet4U.com This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.03 /Jun. 2006 1 HY5DU281622FT(P) Series Revision History Revision No. 0.01 0.02 0.03 First version for internal review State Diagram modified Defined : IDD value History Draft Date Feb. 2006 Apr. 2006 Apr. 2006 Remark www.DataSheet4U.com Rev. 0.03 /Jun. 2006 2 HY5DU281622FT(P) Series DESCRIPTION The HY5DU281622FT(P) is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.