HY5DU281622T-L Datasheet | Hyundai

HY5DU281622 4 Banks x 2M x 16Bit Double Data Rate SDRAM PRELIMINARY DESCRIPTION The Hyundai HY5DU281622 is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY5DU281622 is organized as 4 banks of 2,097,152x16. HY5DU281622 offers fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the clock(falling edges of the CLK), Data(DQ), Data strobes(LDQS/UDQS) and Write data masks(LDM/UDM) inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are patible with SSTL_2. Mode Register set options include the length of pipeline (CAS latency of 2 / 2.5 ), the number of consecutive read or write cycles initiated by a single control mand (Burst length of 2 / 4 / 8), the burst count sequence(sequential or interleave), DQ FET Control (/QFC) and Output Driver types (Full / Half Strength Driver). Because data rate is doubled through reading and writing at both rising and falling edges of the clock, 2X higher data bandwidth can be achieved than that of traditional (single data rate) Synchronous DRAM. Features - - - - - 2.5V V DD and VDDQ power suppliy All inputs and outputs are patible with SSTL_2 interface JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch Fully differential clock operations(CLK & CLK) with 100MHz/125MHz/133MHz All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock Data(DQ) and Write masks(LDM/UDM) latched on both rising and falling edges of the Data Stobe Data outputs on LDQS/UDQS edges when read (edged DQ) Data inputs on LDQS/UDQS centers when write (centered DQ) - - - - - - - - - - Delay Locked Loop(DLL) installed with DLL reset mode...