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HY5DU281622AT Datasheet (hy5du28xxxat) 3rd 128m Ddr Sdram

Manufacturer: SK Hynix

Overview: HY5DU28422A(L)T HY5DU28822A(L)T HY5DU281622A(L)T 3rd 128M DDR SDRAM HY5DU28422A(L)T HY5DU28822A(L)T HY5DU281622A(L)T This document is a general.

This datasheet includes multiple variants, all published together in a single manufacturer document.

General Description

and is subject to change without notice.

Hynix semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Key Features

  • VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL align DQ and DQS transition with CK transition DM mask write data-in at the both ri.

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