HY5DU281622AT Description
and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied.
HY5DU281622AT Key Features
- VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are patible with SSTL_2 interface Fully differential clock inputs (CK,
- data transaction aligned to bidirectional data strobe (DQS) Data outputs on DQS edges when read (edged DQ) Data inputs o
- K -H -L
- X means speed grade -- JEDEC specification pliant