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HY5DU281622AT - (HY5DU28xxxAT) 3rd 128M DDR SDRAM

This page provides the datasheet information for the HY5DU281622AT, a member of the HY5DU28822AT (HY5DU28xxxAT) 3rd 128M DDR SDRAM family.

Product Overview

Hynix Semiconductor

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HY5DU281622AT (HY5DU28xxxAT) 3rd 128M DDR SDRAM by Hynix Semiconductor - Datasheet Preview — Datasheet preview – HY5DU281622AT

Datasheet Details

Part number	HY5DU281622AT
Manufacturer	Hynix Semiconductor
File Size	376.76 KB
Description	(HY5DU28xxxAT) 3rd 128M DDR SDRAM
Datasheet	HY5DU281622AT Datasheet
Additional preview pages of the HY5DU281622AT datasheet.

HY5DU281622AT Product details

Description

and is subject to change without notice.

Hynix semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL align DQ and DQS transition with CK transition DM mask write data-in at the both ri.

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Published: Mar 24, 2006 |