HY5DU281622DT
Overview
- VDD, VDDQ = 2.6V +/- 0.1V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) * * *
- All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock Programmable /CAS latency 2 / 2.5/ 3 supported Programmable burst length 2 / 4 / 8 with both sequential and interleave mode Intern
