HY5DU281622 Description
The Hyundai HY5DU281622 is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY5DU281622 is organized as 4 banks of 2,097,152x16. HY5DU281622 offers fully synchronous operations referenced to both rising and falling edges of the clock.
HY5DU281622 Key Features
- 2.5V V DD and VDDQ power suppliy All inputs and outputs are patible with SSTL_2 interface JEDEC standard 400mil 66pin TS
- Delay Locked Loop(DLL) installed with DLL reset mode Write mask byte controlled by LDM and UDM Bytewide data strobes by
- (L) Low Power Part
- JEDEC Defined Specifications pliant