HY5DU281622ET Datasheet Text
HY5DU281622ET
128M(8Mx16) GDDR SDRAM
HY5DU281622ET
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.5 / Jan. 2005 1
HY5DU281622ET
Revision History
Revision No. 0.1 0.2 0.3 0.4 0.5 Defined target spec. 1) Insert Overshoot/Undershoot Specification 2) Insert tDSS/tDSH Parameter tPDEX value Change tRC_APCG changed to 12 clock from 11 clock at 166Mhz speed bin 166Mhz speed bin delete, AC parameter change (tRC_APCG at 200Mhz) History Draft Date July 2003 Oct. 2003 Mar. 2004 Oct. 2004 Jan. 2005 Remark
Rev. 0.5 / Jan. 2005
2
HY5DU281622ET
DESCRIPTION
The Hynix HY5DU281622ET is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the point-to-point applications which require high densities and high bandwidth. The Hynix 8Mx16 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are patible with SSTL_2.
Features
- -
- -
- -
- - 2.8V +/- 0.1V VDD and VDDQ power supply supports 400/375/350/333/300MHz 2.5V +/- 5% VDD and VDDQ power supply supports 275/250/200/166MHz All inputs and outputs are patible with SSTL_2 interface JEDEC Standard 400 mil x 875 mil 66 Pin TSOP II, with 0.65mm pin pitch Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous
- data...
