* 15 single ended LVCMOS outputs, 7Ω typical output impedance
* Selectable LVCMOS or LVPECL clock inputs
* CLK0 and CLK1 can accept the following input levels.

demanding well defined performance and repeatability. BLOCK DIAGRAM CLK_SEL CLK0 CLK1 PCLK nPCLK PCLK_SEL 1 DIV_SELA 0 .

The ICS87949-01 is a low skew, ÷1, ÷2 Clock Generator and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS87949-01 has selectable single ended clock or LVPECL clock inputs. The single ended clock .

ICS87946-01

ICS87931I

ICS87972I

ICS87972I-147

ICS87973I-147

ICS87974I

ICS87001I-01

ICS87002-05

ICS87004AGT

ICS87004I

ICS87008I

ICS8714008I

ICS87158