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8V19N880 Datasheet

NG Jitter Attenuator and Clock Synthesizer

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FemtoClock® NG Jitter Attenuator
8V19N880
and Clock Synthesizer
Short-Form Datasheet
Description
The 8V19N880 is a fully integrated FemtoClock® NG jitter
attenuator and clock synthesizer designed as a high-performance
clock solution for conditioning and frequency/phase management
of wireless base station radio equipment boards. The device is
optimized to deliver excellent phase noise performance as
required in GSM, WCDMA, LTE, LTE-A, and 5G radio board
implementations. The device supports JESD204B (subclass 0
and 1) and JESD204C.
The 8V19N880 has a two-stage PLL architecture that supports
both jitter attenuation and frequency multiplication. The first stage
PLL is the jitter attenuator and uses an external VCXO for best
possible phase noise characteristics. The second stage PLL locks
on the PLL-0 output signal and synthesizes the target frequency.
The second stage PLL can use the internal or an external
high-frequency VCO.
The 8V19N880 supports the clock generation of high-frequency
clocks from the selected VCO and low-frequency synchronization
signals (SYSREF). SYSREF signals are internally synchronized to
the clock signals. Delay functions exist for achieving alignment
and controlled phase delay between system reference and clock
signals and to align/delay individual output signals. The four
redundant inputs are monitored for activity. Four selectable clock
switching modes are provided to handle clock input failure
scenarios. Auto-lock, individually programmable output frequency
dividers, and phase adjustment capabilities are added for
additional flexibility.
The 8V19N880 is configured through a 3/4-wire SPI interface and
reports lock and signal loss status in internal registers and via the
GPIO[1:0] outputs. Internal status bit changes can also be
reported via a GPIO output. The device is ideal for driving
converter circuits in wireless infrastructure, radar/imaging, and
instrumentation/medical applications. The 8V19N880 is a member
of the high-performance clock family from IDT.
Typical Applications
Wireless infrastructure applications: GSM, WCDMA, LTE,
LTE-A, and 5G
Ideal clock driver for jitter-sensitive ADC and DAC circuits
Low phase noise clock generation
Ethernet line cards
Radar and imaging
Instrumentation and medical
Features
High-performance clock RF-PLL with support for JESD204B/C
Optimized for low phase noise: -150dBc/Hz (800kHz offset;
245.76MHz clock)
Integrated phase noise of < 80fs RMS typical (12k–20MHz)
Dual-PLL architecture with optional external VCO
1st-PLL stage with external VCXO for clock jitter attenuation
2nd-PLL with internal FemtoClockNG PLL: 3932.16MHz
Optional external VCO frequency range: 700MHz–6GHz
Nine output channels with a total of 19 outputs, organized in:
Two RF clock channels each consisting of two device clocks
(4GHz)/SYSREF outputs; each output can buffer external
VCO clocks up to 6GHz
Six device clock/SYSREF channels (2 or 3 outputs, 4GHz
One VCXO-PLL (PLL-0) output
Configurable integer clock frequency dividers
Supported clock output frequencies include:
From internal VCO: 3932.16, 1966.08, 983.04, 491.52, and
245.76MHz
From external VCO: 6GHz
Low-power LVPECL/LVDS outputs support configurable signal
amplitude, DC and AC coupling, and LVPECL, LVDS line
terminations techniques
Phase delay circuits
PLL feedback phase delay for output-to-input alignment
Channel phase delay with 512 steps of 127ps
Individual output phase delay with four steps of 127ps and
additional four steps of 32ps delay for clock/SYSREF
alignment
Redundant input clock architecture with four inputs and
Input activity monitoring
Manual and automatic, fault-triggered clock selection modes
Priority-controlled clock selection
Digital holdover and hitless switching
Differential inputs accept LVDS and LVPECL signals
SYSREF generation modes include internal and external
trigger mode for JESD204B/C
SPI 3/4 wire configuration interface
Supply voltage: 1.8V (core, output) and 3.3V (oscillator
interfaces, 6GHz output supply)
SPI and control I/O voltage: 1.8V
Package: 100-CABGA (11x11 mm²)
Temperature range: -40°C to +95°C (case)
©2019 Integrated Device Technology, Inc.
1
February 19, 2019


Integrated Device Technology Electronic Components Datasheet

8V19N880 Datasheet

NG Jitter Attenuator and Clock Synthesizer

No Preview Available !

Block Diagram
Figure 1. Block Diagram (fVCO = 3932.16MHz)
fVCXO
8V19N880 Short-Form Datasheet
Optional fVCO_EXT
CLK_0
nCLK_0
CLK_1
nCLK_1
CLK_2
nCLK_2
CLK_3
nCLK_3
Clock
Monitor
and
Selector
EXT_SYS
SDAT
MISO
SCLK
nCS
SPI
Register
File
GPIO_[1:0]
ICP_0
nOSC_0 OSC_0
ICP_1
VT_1
nOSC_1
50
50
OSC_1
CP
PLL-0 (VCXO)
CP
0 PLL-1
1 fVCO
BYP_0
00
01
10
11
SRC
SYSREF-Control
GPIO Control
Output Channel A
0
1
Output Channel B
0
1
Output Channel C
0
1
Output Channel D
0
1
0
Output Channel E 1
2
Output Channel F
0
1
Output Channel G
0
1
0
Output Channel H 1
2
Q_VCXO
nQ_VCXO
Q_A0
nQ_A0
Q_A1
nQ_A1
Q_B0
nQ_B0
Q_B1
nQ_B1
Q_C0
nQ_C0
Q_C1
nQ_C1
Q_D0
nQ_D0
Q_D1
nQ_D1
Q_E0
nQ_D0
Q_E1
nQ_D1
Q_E2
nQ_E2
Q_F0
nQ_F0
Q_F1
nQ_F1
Q_D0
nQ_D0
Q_D1
nQ_D1
Q_H0
nQ_H0
Q_H1
nQ_H1
Q_H2
nQ_H2
©2019 Integrated Device Technology, Inc.
2
February 19, 2019


Part Number 8V19N880
Description NG Jitter Attenuator and Clock Synthesizer
Maker IDT
Total Page 3 Pages
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