9DBL0243 - 2-Output 3.3V LP-HCSL Zero-Delay Buffer

Product Overview

IDT

9DBL0243 2-Output 3.3V LP-HCSL Zero-Delay Buffer by IDT - Datasheet Preview — Datasheet preview – 9DBL0243

Datasheet Details

Part number	9DBL0243
Manufacturer	IDT
File Size	350.15 KB
Description	2-Output 3.3V LP-HCSL Zero-Delay Buffer
Datasheet	9DBL0243 Datasheet
Additional preview pages of the 9DBL0243 datasheet.

Product details

Description

The 9DBL0243 / 9DBL0253 devices are 3.3V members of IDT's Full-Featured PCIe clock family. 4 Common Clock (CC) architectures and also support NVLINK applications. PCIe Gen1 4 and NVLINK clock distribution for Riser Cards Storage and Networking JBOD Communications Access Points Output Feat

Features

Loss Of Signal (LOS) open drain output.
2 1.
200 MHz Low-Power (LP) HCSL DIF pairs.
9DBL0243 default Zout = 100Ω.
9DBL0253 default Zout = 85Ω.
Easy AC-coupling to other logic families; see IDT.

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Other Datasheets by IDT

9DBL02 - 2-output 3.3V PCIe Zero-Delay Buffer
9DBL0253 - 2-Output 3.3V LP-HCSL Zero-Delay Buffer
9DBL04 - 4-output 3.3V PCIe Zero-delay Buffer
9DBL0443 - 4-output 3.3V LP-HCSL Zero-Delay Buffer
9DBL0453 - 4-output 3.3V LP-HCSL Zero-Delay Buffer
9DBL0455 - PCIe Gen1-5 Clock Fanout Buffers

Published: Apr 5, 2019 |