9DBL0455
Description
The 9DBL0255/9DBL0455 are 2 and 4-output PCIe clock fanout buffers for PCIe Gen1- 5 applications. Both parts have a open drain Loss of Signal (LOS) output to indicate the absence or presence of an input clock. The devices implement several additional features to aid robust designs. Flexible Power Sequencing (FPS) ensures well-defined behavior under various power up scenarios, while Power Down Tolerant (PDT) ESD protection on all input pins allows input pins to be driven before VDD is applied. The 9DBL0255 and 9DBL0455 are spread spectrum patible and provides direct connection to 85Ω transmission lines. They can also be used in 100Ω environments with simple external series resistors.
PCIe Architectures
- mon Clocked (CC)
- Independent Reference Clock (SRIS, SRn S)
Typical Applications
- PCIe clock distribution in:
- PCIe Riser Cards
- NVME e SSD and JBOD
- High-Performance puting and Accelerators
- Servers
- Ethernet Switches
Features
- 85Ω transmission lines require 0...
