9DBL0452 - 3.3V PCIe Zero Delay Buffer
9DBL0452 Features
* ▪ Four 1
* 200 MHz Low-Power HCSL (LP-HCSL) DIF pairs
* 9DBL0442 default ZOUT = 100Ω
* 9DBL0452 default ZOUT = 85Ω
* 9DBL04P2 factory programmable defaults ▪ Easy AC-coupling to other logic families, see Renesas application note AN-891 Key Specifications ▪ PCIe Gen1
