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Integrated Device Technology Electronic Components Datasheet

IDT71V35761S Datasheet

3.3V Synchronous SRAMs

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128K x 36
3.3V Synchronous SRAMs
IDT71V35761S/SA
3.3V I/O, Pipelined Outputs
Burst Counter, Single Cycle Deselect
Features
128K x 36 memory configurations
Supports high system speed:
Commercial:
– 200MHz 3.1ns clock access time
Commercial and Industrial:
– 183MHz 3.3ns clock access time
– 166MHz 3.5ns clock access time
LBO input selects interleaved or linear burst mode
3.3V core power supply
Functional Block Diagram
LBO
ADV
CLK
ADSC
ADSP
Self-timed write cycle with global write control (GW), byte
write enable (BWE), and byte writes (BWx)
Power down controlled by ZZ input
3.3V I/O
Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine
pitch ball grid array
Green parts available, see ordering information
CEN
Binary
Counter
CLR
2
Burst
Sequence
Burst
Logic
Q0
Q1
A0*
A1*
INTERNAL
ADDRESS
17/18
128K x 36-
BIT
MEMORY
ARRAY
A0 - A16/17
GW
BWE
BW1
BW2
BW3
BW4
CE
CS0
CS1
CLK EN
ADDRESS
REGISTER
Byte 1
Write Register
Byte 2
Write Register
Byte 3
Write Register
Byte 4
Write Register
DQ
Enable
Register
CLK EN
17/18
2
A0,A1
A2–A17
36 36
Byte 1
Write Driver
9
Byte 2
Write Driver
9
Byte 3
Write Driver
9
Byte 4
Write Driver
9
OUTPUT
REGISTER
DATA
INPUT
REGISTER
ZZ Powerdown
OE
I/O0 — I/O31
I/OP1 — I/OP4
36
TMS
TDI
TCK
TRST
(Optional)
©2014 Integrated Device Technology, Inc.
DQ
Enable
Delay
Register
JTAG
(SA Version)
TDO
1
OE OUTPUT
BUFFER
,
5301 drw 01
NOVEMBER 2014
DSC-5301/07


Integrated Device Technology Electronic Components Datasheet

IDT71V35761S Datasheet

3.3V Synchronous SRAMs

No Preview Available !

IDT71V357611,1 128K x 36, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Description
The IDT71V35761 are high-speed SRAMs organized as
128K x 36. The IDT71V35761 SRAMs contain write, data, address and
controlregisters. InternallogicallowstheSRAMtogenerateaself-timed
write based upon a decision which can be left until the end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V35761 can provide four cycles of data for
a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating
the access sequence. The first cycle of output data will be pipelined
for one cycle before it is available on the next rising clock edge. If
burst mode operation is selected (ADV=LOW), the subsequent
three cycles of output data will be available to the user on the next
three rising clock edges. The order of these three addresses are
defined by the internal burst counter and the LBO input pin.
The IDT71V35761 SRAMs utilize a high-performance CMOS
process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array(fBGA).
Pin Description Summary
A0-A17
Address Inputs
CE Chip Enable
CS0, CS1
Chip Selects
OE Output Enable
GW Global Write Enable
BWE Byte Write Enable
BW1, BW2, BW3, BW4(1)
Individual Byte Write Selects
CLK Clock
ADV Burst Address Advance
ADSC
Address Status (Cache Controller)
ADSP
Address Status (Processor)
LBO Linear / Interleaved Burst Order
TMS Test Mode Select
TDI Test Data Input
TCK Test Clock
TDO Test Data Output
TRST
JTAG Reset (Optional)
ZZ Sleep Mode
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
VDD, VDDQ
Core Power, I/O Power
VSS Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Synchronous
Synchronous
N/A
Synchronous
Asynchronous
Asynchronous
Synchronous
N/A
N/A
5301 tbl 01
6.422


Part Number IDT71V35761S
Description 3.3V Synchronous SRAMs
Maker IDT
Total Page 21 Pages
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