IDT71V35761S Overview
The IDT71V35761 are high-speed SRAMs organized as 128K x 36. The IDT71V35761 SRAMs contain write, data, address and controlregisters. InternallogicallowstheSRAMtogenerateaself-timed write based upon a decision which can be left until the end of the write cycle.
IDT71V35761S Key Features
- 128K x 36 memory configurations
- Supports high system speed
- 200MHz 3.1ns clock access time mercial and Industrial
- 183MHz 3.3ns clock access time
- 166MHz 3.5ns clock access time
- LBO input selects interleaved or linear burst mode
- 3.3V core power supply
- Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx)
- Power down controlled by ZZ input
- 3.3V I/O
