IDT71V35761SA - 128K x 36 3.3V Synchronous SRAM

This page provides the datasheet information for the IDT71V35761SA, a member of the IDT71V35761S 128K x 36 3.3V Synchronous SRAM family.

Product Overview

Renesas

Part number	IDT71V35761SA
Manufacturer	Renesas
File Size	1.16 MB
Description	128K x 36 3.3V Synchronous SRAM
Datasheet	IDT71V35761SA Datasheet
Additional preview pages of the IDT71V35761SA datasheet.

The IDT71V35761 are high-speed SRAMs organized as 128K x 36.

The IDT71V35761 SRAMs contain write, data, address and controlregisters.

InternallogicallowstheSRAMtogenerateaself-timed write based upon a decision which can be left until the end of the write cycle.

128K x 36 memory configurations.
Supports high system speed: Commercial:.
200MHz 3.1ns clock access time Commercial and Industrial:.
183MHz 3.3ns clock access time.
166MHz 3.5ns clock access time.
LBO input selects interleaved or linear burst mode.
3.3V core power supply Functional Block Diagram LBO ADV CLK ADSC ADSP.
Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx).
Power down control.

Other Datasheets by Renesas

Published: Feb 27, 2020 |