IDT71V3576S Description
The IDT71V3576/78 are high-speed SRAMs organized as 128K x 36/256K x 18. The IDT71V3576/78 SRAMs contain write, data, addressandcontrolregisters. InternallogicallowstheSRAMtogenerate a self-timed write based upon a decision which can be left until the end of the write cycle.
IDT71V3576S Key Features
- 128K x 36, 256K x 18 memory configurations
- Supports high system speed
- 150MHz 3.8ns clock access time
- 133MHz 4.2ns clock access time
- LBO input selects interleaved or linear burst mode
- Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx)
- 3.3V core power supply
- Power down controlled by ZZ input
- 3.3V I/O
- Packaged in a JEDEC Standard 100-pin plastic thin quad flatpack (TQFP)