IDT71V35781S Overview
Summary Description The IDT71V35761/781 are high-speed SRAMs organized as 128K x 36/256K x 18. The IDT71V35761/781 SRAMs contain write, data, addressandcontrolr.
IDT71V35781S Key Features
- 200MHz 3.1ns clock access time mercial and Industrial
- 183MHz 3.3ns clock access time
- 166MHz 3.5ns clock access time x LBO input selects interleaved or linear burst mode x Self-timed write cycle with global
- Boundary Scan JTAG Interface (IEEE 1149.1 pliant) x Packaged in a JEDEC Standard 100-pin plastic thin quad flatpack (TQF