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Integrated Device Technology Electronic Components Datasheet

IDT71V35781SA Datasheet

3.3V Synchronous SRAMs

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128K x 36, 256K x 18
3.3V Synchronous SRAMs
3.3V I/O, Pipelined Outputs
Burst Counter, Single Cycle Deselect
IDT71V35761S
IDT71V35781S
IDT71V35761SA
IDT71V35781SA
Features
x 128K x 36, 256K x 18 memory configurations
x Supports high system speed:
Commercial:
– 200MHz 3.1ns clock access time
Commercial and Industrial:
– 183MHz 3.3ns clock access time
– 166MHz 3.5ns clock access time
x LBO input selects interleaved or linear burst mode
x Self-timed write cycle with global write control (GW), byte write
enable (BWE), and byte writes (BWx)
x 3.3V core power supply
x Power down controlled by ZZ input
x 3.3V I/O
x Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
x Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array
Pin Description Summary
Description
The IDT71V35761/781 are high-speed SRAMs organized as
128K x 36/256K x 18. The IDT71V35761/781 SRAMs contain write, data,
addressandcontrolregisters. InternallogicallowstheSRAMtogenerate
a self-timed write based upon a decision which can be left until the end of
the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V35761/81 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
datawillbeavailabletotheuseronthenextthreerisingclockedges. The
order of these three addresses are defined by the internal burst counter
and the LBO input pin.
The IDT71V35761/781 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array.
A0-A17
Address Inputs
Input Synchronous
CE Chip Enable
Input Synchronous
CS0, CS1
Chip Selects
Input Synchronous
OE Output Enable
Input Asynchronous
GW Global Write Enable
Input Synchronous
BWE Byte Write Enable
Input Synchronous
BW1, BW2, BW3, BW4(1)
Individual Byte Write Selects
Input Synchronous
CLK Clock
Input N/A
ADV Burst Address Advance
Input Synchronous
ADSC
Address Status (Cache Controller)
Input Synchronous
ADSP
Address Status (Processor)
Input Synchronous
LBO Linear / Interleaved Burst Order
Input DC
TMS Test Mode Select
Input Synchronous
TDI Test Data Input
Input Synchronous
TCK Test Clock
Input N/A
TDO Test Data Output
Output
Synchronous
TRST
JTAG Reset (Optional)
Input Asynchronous
ZZ Sleep Mode
Input Asynchronous
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
I/O Synchronous
VDD, VDDQ
Core Power, I/O Power
Supply
N/A
NVOSTSE:
Ground
1. BW3 and BW4 are not applicable for the IDT71V35781.
©2003 Integrated Device Technology, Inc.
1
Supply
N/A
5301 tbl 01
JUNE 2003
DSC-5301/03


Integrated Device Technology Electronic Components Datasheet

IDT71V35781SA Datasheet

3.3V Synchronous SRAMs

No Preview Available !

IDT71V357611,1IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Definitions(1)
Symbol
Pin Function
I/O
Active
Description
A0-A17
ADSC
Address Inputs
Address Status
(Cache Controller)
I
I
N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK
and ADSC Low or ADSP Low and CE Low.
LOW Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is used to load the
address registers with new addresses.
ADSP
ADV
Address Status
(Processor)
Burst Address
Advance
I LOW Synchronous Address Status from Processor. ADSP is an active LOW input that is used to load the address
registers with new addresses. ADSP is gated by CE.
I LOW Synchronous Address Advance. ADV is an active LOW input that is used to advance the internal burst
counter, controlling burst access after the initial address is loaded. When the input is HIGH the burst counter is
not incremented; that is, there is no address advance.
BWE
Byte Write Enable
I
BW1-BW4
Individual Byte
Write Enables
I
LOW Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the rising edge of CLK
then BWx inputs are passed to the next stage in the circuit. If BWE is HIGH then the byte write inputs are
blocked and only GW can initiate a write cycle.
LOW Synchronous byte write enables. BW1 controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc. Any active byte
write causes all outputs to be disabled.
CE
Chip Enable
I LOW Synchronous chip enable. CE is used with CS0 and CS1 to enable the IDT71V35761/781. CE also gates
ADSP.
CLK
Clock
I N/A This is the clock input. All timing references for the device are made with respect to this input.
CS0
Chip Select 0
I HIGH Synchrono us active HIGH chip select. CS0 is used with CE and CS1 to enable the chip.
CS1
Chip Select 1
I LOW Synchronous active LOW chip select. CS1 is used with CE and CS0 to enable the chip.
GW
Global Write
I LOW Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising edge of
Enable
CLK. GW supersedes individual byte write enables.
I/O0-I/O31
I/OP1-I/OP4
LBO
Data Input/Output
Linear Burst Order
I/O
I
N/A Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and
triggered by the rising edge of CLK.
LOW Asynchronous burst order selection input. When LBO is HIGH, the interleaved burst sequence is selected.
When LBO is LOW the Line ar burst sequence is selected. LBO is a static input and must not change state
while the device is operating.
OE
Output Enable
I LOW Asynchronous output enable. When OE is LOW the data output drivers are enabled on the I/O pins if the chip
is also selected. When OE is HIGH the I/O pins are in a high-impedance state.
TMS
Test ModeSelect
I
N/A Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
TDI
Test Data Input
I
N/A
Serial input of registers placed be tween TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.
TCK
Test Clock
I
N/A
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,
while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
TDO
Test DataOutput
O
N/A
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the
TAP controller.
TRST
JTAG Reset
(Optional)
Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset
I LOW occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can
be left floating. This pin has an inte rnal pullup. Only available in BGA package.
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V35761/35781
ZZ
Sleep Mode
I HIGH to its lowest power consumption level. Data retention is guaranteed in Slee p Mode.This pin has an internal
pull down.
VDD Power Supply N/A N/A 3.3V core power supply.
VDDQ Power Supply N/A N/A 3.3V I/O Supply.
VSS
Ground
N/A N/A Ground.
NC
No Connect
N/A N/A NC pins are not electrically connected to the device.
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
5301tbl 02
6.422


Part Number IDT71V35781SA
Description 3.3V Synchronous SRAMs
Maker IDT
Total Page 22 Pages
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