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IDT71V35781SA - 3.3V Synchronous SRAMs

This page provides the datasheet information for the IDT71V35781SA, a member of the IDT71V35761S 3.3V Synchronous SRAMs family.

Datasheet Summary

Description

The IDT71V35761/781 are high-speed SRAMs organized as 128K x 36/256K x 18.

Features

  • x 128K x 36, 256K x 18 memory configurations x Supports high system speed: Commercial:.
  • 200MHz 3.1ns clock access time Commercial and Industrial:.
  • 183MHz 3.3ns clock access time.
  • 166MHz 3.5ns clock access time x LBO input selects interleaved or linear burst mode x Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) x 3.3V core power supply x Power down controlled by ZZ input x 3.3V I/O x Optional - Boundary Scan JTAG In.

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Datasheet preview – IDT71V35781SA

Datasheet Details

Part number IDT71V35781SA
Manufacturer IDT
File Size 280.18 KB
Description 3.3V Synchronous SRAMs
Datasheet download datasheet IDT71V35781SA Datasheet
Additional preview pages of the IDT71V35781SA datasheet.

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Full PDF Text Transcription

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128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect IDT71V35761S IDT71V35781S IDT71V35761SA IDT71V35781SA Features x 128K x 36, 256K x 18 memory configurations x Supports high system speed: Commercial: – 200MHz 3.1ns clock access time Commercial and Industrial: – 183MHz 3.3ns clock access time – 166MHz 3.5ns clock access time x LBO input selects interleaved or linear burst mode x Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) x 3.3V core power supply x Power down controlled by ZZ input x 3.3V I/O x Optional - Boundary Scan JTAG Interface (IEEE 1149.
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