IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
I/O Active Description
Synchronous Address inputs. The address register is triggered by a combination of the rising edge
of CLK and ADSC Low or ADSP Low and CE Low.
Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is used to load
the address registers with new addresses.
Synchronous Address Status from Processor. ADSP is an active LOW input that is used to load the
address registers with new addresses. ADSP is gated by CE.
Synchronous Address Advance. ADV is an active LOW input that is used to advance the internal
I LOW burst counter, controlling burst access after the initial address is loaded. When the input is HIGH the
burst counter is not incremented; that is, there is no address advance.
Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the rising
BWE Byte Write Enable I LOW edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is HIGH then the
byte write inputs are blocked and only GW can initiate a write cycle.
Synchronous byte write enables. BW1 controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc. Any
active byte write causes all outputs to be disabled.
Synchronous chip enable. CE is used with CS0 and CS1 to enable the IDT71V3576/78. CE also gates
I N/A This is the clock input. All timing references for the device are made with respect to this input.
Chip Select 0
I HIGH Synchronous active HIGH chip select. CS0 is used with CE and CS1 to enable the chip.
Chip Select 1
I LOW Synchronous active LOW chip select. CS1 is used with CE and CS0 to enable the chip.
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising
edge of CLK. GW supersedes individual byte write enables.
Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered
and triggered by the rising edge of CLK.
Asynchronous burst order selection input. When LBO is HIGH, the interleaved burst sequence is
Linear Burst Order
LOW selected. When LBO is LOW the Linear burst sequence is selected. LBO is a static input and must
not change state while the device is operating.
Asynchronous output enable. When OE is LOW the data output drivers are enabled on the I/O pins if
the chip is also selected. When OE is HIGH the I/O pins are in a high-impedance state.
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
I HIGH IDT71V3576/78 to its lowest power consumption level. Data retention is guaranteed in Sleep
Mode.This pin has an internal pull down.
N/A N/A 3.3V core power supply.
N/A N/A 3.3V I/O Supply.
N/A N/A Ground.
N/A N/A NC pins are not electrically connected to the device.
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
5279 tbl 02