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IDT71V35761S - 3.3V Synchronous SRAMs

This page provides the datasheet information for the IDT71V35761S, a member of the IDT71V35761SA 3.3V Synchronous SRAMs family.

Datasheet Summary

Features

  • 128K x 36 memory configurations.
  • Supports high system speed: Commercial:.
  • 200MHz 3.1ns clock access time Commercial and Industrial:.
  • 183MHz 3.3ns clock access time.
  • 166MHz 3.5ns clock access time.
  • LBO input selects interleaved or linear burst mode.
  • 3.3V core power supply Functional Block Diagram LBO ADV CLK ADSC ADSP.
  • Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx).
  • Power down control.

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Datasheet preview – IDT71V35761S

Datasheet Details

Part number IDT71V35761S
Manufacturer IDT
File Size 818.92 KB
Description 3.3V Synchronous SRAMs
Datasheet download datasheet IDT71V35761S Datasheet
Additional preview pages of the IDT71V35761S datasheet.

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Full PDF Text Transcription

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128K x 36 3.3V Synchronous SRAMs IDT71V35761S/SA 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect Features ◆ 128K x 36 memory configurations ◆ Supports high system speed: Commercial: – 200MHz 3.1ns clock access time Commercial and Industrial: – 183MHz 3.3ns clock access time – 166MHz 3.5ns clock access time ◆ LBO input selects interleaved or linear burst mode ◆ 3.3V core power supply Functional Block Diagram LBO ADV CLK ADSC ADSP ◆ Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) ◆ Power down controlled by ZZ input ◆ 3.3V I/O ◆ Optional - Boundary Scan JTAG Interface (IEEE 1149.
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