IDT71V3556SA - 3.3V Synchronous ZBT SRAMs

This page provides the datasheet information for the IDT71V3556SA, a member of the IDT-71V 3.3V Synchronous ZBT SRAMs family.

Product Overview

Integrated Device Technology

Part number	IDT71V3556SA
Manufacturer	Integrated Device Technology
File Size	477.21 KB
Description	3.3V Synchronous ZBT SRAMs
Datasheet	IDT71V3556SA Datasheet
Additional preview pages of the IDT71V3556SA datasheet.

The IDT71V3556/58 are 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAMS.

They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads.

Thus, they have been given the name ZBTTM, or Zero Bus Turnaround.

128K x 36, 256K x 18 memory configurations Supports high performance system speed - 200 MHz (3.2 ns Clock-to-Data Access) ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized output buffer enable eliminates the need to control OE Single R/W (READ/WRITE) control pin Positive clock-edge triggered address, data, and control signal registers for fully pipelined.

Other Datasheets by Integrated Device Technology

Published: Apr 5, 2005 |