IDT71V546S - 3.3V Synchronous SRAM

Datasheet Details

128K x 36 memory configuration, pipelined outputs.
Supports high performance system speed - 133 MHz (4.2 ns Clock-to-Data Access).
ZBTTM Feature - No dead cycles between write and read cycles.
Internally synchronized registered outputs eliminate the need to control OE.
Single R/W (READ/WRITE) control pin Functional Block Diagram LBO Address A [0:16] CE1, CE2, CE2 R/W CEN ADV/LD BWx DQ DQ.
Positive clock-edge triggered address, data, and control signal registers.

📁 IDT71V546S Similar Datasheet

IDT71V546 - 128K x 36/ 3.3V Synchronous SRAM with ZBT Feature/ Burst Counter and Pipelined Outputs (Integrated Device Technology)
IDT71V509 - 128K x 8 3.3V SYNCHRONOUS SRAM WITH ZBTO AND FLOW-THROUGH OUTPUT (Integrated Device Technology)
IDT71V016SA - 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) (Integrated Device Technology)
IDT71V124SA - 3.3V CMOS Static RAM (Renesas)
IDT71V2546SA - 128K x 36/ 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O/ Burst Counter Pipelined Outputs (Integrated Device Technology)
IDT71V2548S - 128K x 36/ 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O/ Burst Counter Pipelined Outputs (Integrated Device Technology)
IDT71V2548SA - 128K x 36/ 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O/ Burst Counter Pipelined Outputs (Integrated Device Technology)
IDT71V2558S - 3.3V Synchronous ZBT SRAMs 2.5V I/O (Integrated Device Technology)

Other Datasheets by IDT

Published: Apr 7, 2019 |