IDT71V546 Overview
The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAM organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turn-around.
IDT71V546 Key Features
- 133 MHz (4.2 ns Clock-to-Data Access) ZBTTM Feature
- No dead cycles between write and read cycles Internally synchronized registered outputs eliminate the need to control OE
