IDT71V546S Overview
The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAM organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turn-around.
IDT71V546S Key Features
- 128K x 36 memory configuration, pipelined outputs
- Supports high performance system speed
- 133 MHz
- ZBTTM Feature
- No dead cycles between write and read
- Internally synchronized registered outputs eliminate the
- Single R/W (READ/WRITE) control pin
- Positive clock-edge triggered address, data, and control signal registers for fully pipelined
