IDT71V546S Datasheet Synchronous SRAM

Manufacturer: Renesas

Datasheet Details

The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAM organized as 128K x 36 bits.

It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads.

Thus it has been given the name ZBTTM, or Zero Bus Turn-around.

128K x 36, 3.3V Synchronous IDT71V546S SRAM with ZBT™ Feature Burst Counter and Pipelined.

128K x 36 memory configuration, pipelined outputs.
Supports high performance system speed - 133 MHz (4.2 ns Clock-to-Data Access).
ZBTTM Feature - No dead cycles between write and read cycles.
Internally synchronized registered outputs eliminate the need to control OE.
Single R/W (READ/WRITE) control pin Functional Block Diagram LBO Address A [0:16] CE1, CE2, CE2 R/W CEN ADV/LD BWx DQ DQ.
Positive clock-edge triggered address, data, and control signal registers.

Brand Logo	Part Number	Description	Manufacturer
	IDT71V546S	3.3V Synchronous SRAM	IDT
	IDT71V546	128K x 36/ 3.3V Synchronous SRAM with ZBT Feature/ Burst Counter and Pipelined Outputs	Integrated Device Technology