IDT71V547S - 3.3V Synchronous SRAM

Datasheet Details

128K x 36 memory configuration, flow-through outputs.
Supports high performance system speed - 95 MHz (8ns Clock-to-Data Access).
ZBTTM Feature - No dead cycles between write and read cycles.
Internally synchronized signal eliminates the need to control OE Functional Block Diagram LBO Address A [0:16] CE1, CE2, CE2 R/W CEN ADV/LD BWx DQ DQ.
Single R/W (READ/WRITE) control pin.
4-word burst capability (Interleaved or linear).
Individual byte write (BW1 - BW4.

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Published: Apr 7, 2019 |