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IS46DR16128C - DDR2 DRAM

Download the IS46DR16128C datasheet PDF. This datasheet also covers the IS46DR82560C variant, as both devices belong to the same ddr2 dram family and are provided as variant models within a single manufacturer datasheet.

Description

ISSI's 2Gb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation.

The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls.

Features

  • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V.
  • JEDEC standard 1.8V I/O (SSTL_18-compatible).
  • Double data rate interface: two data transfers per clock cycle.
  • Differential data strobe (DQS, DQS).
  • 4-bit prefetch architecture.
  • On chip DLL to align DQ and DQS transitions with CK.
  • 8 internal banks for concurrent operation.
  • Programmable CAS latency (CL) 3, 4, 5, 6, and 7 supported.
  • Posted CAS and programmable additive latency (AL).

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS46DR82560C-ISSI.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription

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IS43/46DR82560C IS43/46DR16128C 256Mx8, 128Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.
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