IS46DR16128C
FEATURES
- Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
- JEDEC standard 1.8V I/O (SSTL_18-patible)
- Double data rate interface: two data transfers per clock cycle
- Differential data strobe (DQS, DQS)
- 4-bit prefetch architecture
- On chip DLL to align DQ and DQS transitions with CK
- 8 internal banks for concurrent operation
- Programmable CAS latency (CL) 3, 4, 5, 6, and
7 supported
- Posted CAS and programmable additive latency
(AL) 0, 1, 2, 3, 4, 5, and 6 supported
- WRITE latency = READ latency
- 1 t CK
- Programmable burst lengths: 4 or 8
- Adjustable data-output drive strength, full and reduced strength options
- On-die termination (ODT)
OPTIONS
- Configuration(s):
256Mx8 (32Mx8x8 banks) IS43/46DR82560C 128Mx16 (16Mx16x8 banks) IS43/46DR16128C
- Package: x8: 60-ball BGA (8mm x 10.5mm) x16: 84-ball WBGA (8mm x 12.5mm) Timing
- Cycle time 2.5ns @CL=5 DDR2-800D 3.0ns @CL=5 DDR2-667D
- Temperature Range: mercial (0°C ≤ Tc ≤ 85°C) Industrial (-40°C ≤ Tc ≤ 95°C; -40°C ≤ Ta ≤ 85°C)...
