| Title | |
| Description | at page 6 for each ODT option. DESCRIPTION The 72Mb IS61DDPB22M36C/C1/C2 and IS61DDPB24M18 C/C1/C2 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of ... |
| Features |
2Mx36 and 4Mx18 configuration available. Common I/O read and write ports. Max. 567 MHz clock for high bandwidth Synchronous pipeline read with self-timed late write operation. Double Data Rate (DDR) interface for read and write input ports. 2.5 cycle read latency. Fixed 2-bit burst for read and write operations. Two input clocks (K ... |
| Datasheet |
 IS61DDPB24M18C1 Datasheet - 851.41KB |
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