IS61DDPB24M18C1
FEATURES
- 2Mx36 and 4Mx18 configuration available.
- mon I/O read and write ports.
- Max. 567 MHz clock for high bandwidth
- Synchronous pipeline read with self-timed late write operation.
- Double Data Rate (DDR) interface for read and write input ports.
- 2.5 cycle read latency.
- Fixed 2-bit burst for read and write operations.
- Two input clocks (K and K#) for address and control registering at rising edges only.
- Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
- +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.
- HSTL input and output interface.
- Full data coherency.
- On-chip Delay-Locked Loop (DLL) for wide data valid window.
- Boundary scan using limited set of JTAG 1149.1 functions.
- Byte write capability.
- Fine ball grid array (FBGA) package:
13mm x 15mm & 15mm x 17mm body size 165-ball (11 x 15) array
- Programmable impedance output drivers via 5x user-supplied precision resistor.
- Data Valid Pin (QVLD).
- ODT (On Die...
