IS61NLF102418 sram equivalent, state bus sram.
DESCRIPTION
* 100 percent bus utilization
* No wait cycles between Read and Write
* Internal self-timed write cycle
* Individual Byte Write Control
.
They are organized as 256K words by 72 bits, 512K words
by 36 bits and 1M words by 18 bits, fabricated with ISSI's
adv.
Image gallery
Download