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IS61NVF102436A - 36Mb STATE BUS SRAM

Download the IS61NVF102436A datasheet PDF (IS61NLF102436A included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 36mb state bus sram.

Description

The 36 Meg 'NLF/NVF' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications.

Features

  • 100 percent bus utilization.
  • No wait cycles between Read and Write.
  • Internal self-timed write cycle.
  • Individual Byte Write Control.
  • Single Read/Write control pin.
  • Clock controlled, registered address, data and control.
  • Interleaved or linear burst sequence control us- ing MODE input.
  • Three chip enables for simple depth expansion and address pipelining.
  • Power Down mode.
  • Common data inputs and data outputs.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61NLF102436A-ISSI.pdf) that lists specifications for multiple related part numbers.

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Full PDF Text Transcription

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IS61NLF102436A/IS61NVF102436A IS61NLF204818A/IS61NVF204818A  1M x 36 and 2M x 18 36Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM FEBRUARY 2012 FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single Read/Write control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control us- ing MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP package • Power supply: NVF: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NLF: Vdd 3.3V (± 5%), Vddq 3.3V/2.
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