| Title | |
| Description | at page 6 for each ODT option. DESCRIPTION The IS61QDPB22M36C/C1/C2 and IS61QDPB24M18C/C1/ -C2 are 72Mb synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the descriptio... |
| Features |
2Mx36 and 4Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window. Separate independent read and write ports with concurrent read and write operations. Max. 450 MHz clock for high bandwidth Synchronous pipeline read with EARLY write operation. Double Data Rate (DDR) interface for read and write input po... |
| Datasheet |
 IS61QDPB24M18C1 Datasheet - 756.28KB |
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