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IS61QDPB24M18C1 - 72Mb QUADP Synchronous SRAM

Download the IS61QDPB24M18C1 datasheet PDF. This datasheet also covers the IS61QDPB24M18C variant, as both devices belong to the same 72mb quadp synchronous sram family and are provided as variant models within a single manufacturer datasheet.

General Description

at page 6 for each ODT option.

The IS61QDPB22M36C/C1/C2 and IS61QDPB24M18C/C1/ -C2 are 72Mb synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.

Key Features

  • 2Mx36 and 4Mx18 configuration available.
  • On-chip Delay-Locked Loop (DLL) for wide data valid window.
  • Separate independent read and write ports with concurrent read and write operations.
  • Max. 450 MHz clock for high bandwidth.
  • Synchronous pipeline read with EARLY write operation.
  • Double Data Rate (DDR) interface for read and write input ports.
  • 2.5 Cycle read latency.
  • Fixed 2-bit burst for read and write operations.
  • Two input clocks (K and K#) fo.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61QDPB24M18C-ISSI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
IS61C1024 128K x 8 HIGH-SPEED CMOS STATIC RAM Integrated Silicon Solution
IS61C1024L 128K x 8 HIGH-SPEED CMOS STATIC RAM Integrated Silicon Solution
IS61C256 32K x 8 Low Voltage CMOS STATIC RAM Integrated Silicon Solution
IS61C25616 256K x 8 High Speed CMOS STATIC RAM Integrated Silicon Solution
IS61C25616AL 256K x 16 HIGH-SPEED CMOS STATIC RAM Integrated Silicon Solution

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61QDPB24M18C 72Mb QUADP Synchronous SRAM
IS61QDPB24M18C2 72Mb QUADP Synchronous SRAM
IS61QDPB24M18A 72Mb QUADP (Burst 2) Synchronous SRAM
IS61QDPB24M18A1 72Mb QUADP (Burst 2) Synchronous SRAM
IS61QDPB24M18A2 72Mb QUADP (Burst 2) Synchronous SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS61QDPB24M18C/C1/C2 IS61QDPB22M36C/C1/C2 4Mx18, 2Mx36 72Mb QUADP (Burst 2) Synchronous SRAM (2.5 CYCLE READ LATENCY) APRIL 2018 FEATURES  2Mx36 and 4Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Max. 450 MHz clock for high bandwidth  Synchronous pipeline read with EARLY write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.5 Cycle read latency.  Fixed 2-bit burst for read and write operations.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  Data valid pin (QVLD).  +1.8V core power supply and 1.5, 1.