IS61QDPB24M18C1 Description
at page 6 for each ODT option. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.
IS61QDPB24M18C1 Key Features
- 2Mx36 and 4Mx18 configuration available
- On-chip Delay-Locked Loop (DLL) for wide data valid window
- Separate independent read and write ports with concurrent read and write operations
- Max. 450 MHz clock for high bandwidth
- Synchronous pipeline read with EARLY write operation
- Double Data Rate (DDR) interface for read and write input ports
- 2.5 Cycle read latency
- Fixed 2-bit burst for read and write operations
- Two input clocks (K and K#) for address and control registering at rising edges only
- Two echo clocks (CQ and CQ#) that are delivered simultaneously with data