ICS83056I-01 Datasheet | Integrated Circuit Systems

DESCRIPTION The ICS83056I-01 is a 6-bit, 2:1, Single-ended Multiplexer and a member of the Hi Per Clock S™fam Hi Per Clock S™ ily of High Performance Clock Solutions from ICS. The ICS83056I-01 has two selectable single-ended clock inputs and six single-ended clock outputs. The output has a VDDO pin which may be set at 3.3V, 2.5V, or 1.8V, making the device ideal for use in voltage translation applications. An output enable pin places the output in a high impedance state which may be useful for testing or .. debug. Possible applications include systems with up to 6 transceivers which need to be independently set for different rates. For example, a board may have six transceivers, each of which need to be independently configured for 1 Gigabit Ethernet or 1 Gigabit Fibre Channel rates. Another possible application may require the ports to be independently set for FEC (Forward Error Correction) or non-FEC rates. The device operates up to 250MHz and is packaged in a 20 TSSOP. FEATURES - 6-bit, 2:1 single-ended multiplexer - Nominal output impedance: 15Ω (VDDO =3 .3V) - Maximum output frequency: 250MHz - Propagation delay: 2.5ns (typical) - Input skew: 45ps (typical) - Part-to-part skew: TBD - Additive phase jitter, RMS (12KHz - 20MHz): 0.07ps (typical) - Operating supply modes: VDD/VDDO 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V - -40°C to 85°C ambient operating temperature BLOCK DIAGRAM SEL0 Pulldown PIN ASSIGNMENT SEL5 Q5 VDDO GND Q4 SEL4 CLK1 VDD Q3 SEL3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 SEL0 Q0 VDDO GND Q1 SEL1 CLK0 OE Q2 SEL2 CLK0 Pulldown Q0 CLK1 Pulldown Q5 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top View SEL5 Pulldown OE Pullup The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry...