differential-to-lvcmos/lvttl clock generator.
* Fully integrated PLL
* 9 LVCMOS/LVTTL outputs, 7Ω typical output impedance
* CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS.
the maximum voltage for CLK, nCLK is VDD + 0.3V.
8602BY
www.icst.com/products/hiperclocks.html
3
REV. F APRIL 16, 200.
The ICS8602 is a high performance, low skew, ,&6 1-to-9 Differential-to-LVCMOS/LVTTL Zero DeHiPerClockS™ lay Buffer and a member of the HiPerClockS™ family of High Performance Clocks Solutions from ICS. The CLK, nCLK pair can accept most standard dif.
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