900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf






Integrated Circuit Systems

ICS93701 Datasheet Preview

ICS93701 Datasheet

DDR Phase Lock Loop Clock Driver

No Preview Available !

www.DataSheet.co.kr
Integrated
Circuit
Systems, Inc.
ICS9370 1
DDR Phase Lock Loop Clock Driver
Recommended Application:
DDR Clock Driver
Product Description/Features:
• Low skew, low jitter PLL clock driver
• I2C for functional and output control
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
Switching Characteristics:
• PEAK - PEAK jitter (66MHz): <120ps
• PEAK - PEAK jitter (>100MHz): <75ps
• CYCLE - CYCLE jitter (66MHz):<120ps
• CYCLE - CYCLE jitter (>100MHz):<65ps
• OUTPUT - OUTPUT skew: <100ps
• DUTY CYCLE: 49.5% - 50.5%
• Slew rate: 1V/ns - 2V/ns
Pin Configuration
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
GND
CLKC2
CLKT2
VDD
SCLK
CLK_INT
CLK_INC
VDDI2C
AVDD
AGND
GND
CLKC3
CLKT3
VDD
CLKT4
CLKC4
GND
1 48 GND
2 47 CLKC5
3 46 CLKT5
4 45 VDD
5 44 CLKT6
6 43 CLKC6
7 42 GND
8 41 GND
9 40 CLKC7
10 39 CLKT7
11 38 VDD
12 37 SDATA
13 36 FB_INC
14 35 FB_INT
15 34 VDD
16 33 FB_OUTT
17 32 FB_OUTC
18 31 GND
19 30 CLKC8
20 29 CLKT8
21 28 VDD
22 27 CLKT9
23 26 CLKC9
24 25 GND
48-Pin TSSOP
Block Diagram
SCLK
SDATA
Control
Logic
FB_INT
FB_INC
CLK_INC
CLK_INT
PLL
0417B—10/29/02
FB_OUTT
FB_OUTC
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
Functionality
AVDD
2.5V
(nom)
2.5V
(nom)
2.5V
(nom)
INPUTS
CLK_INT CLK_INC
LH
HL
<20MHz)(1)
OUTPUTS
CLKT CLKC FB_OUTT
LH
L
HL
H
ZZ
Z
FB_OUTC
H
L
Z
PLL State
on
on
off
Datasheet pdf - http://www.DataSheet4U.net/




Integrated Circuit Systems

ICS93701 Datasheet Preview

ICS93701 Datasheet

DDR Phase Lock Loop Clock Driver

No Preview Available !

www.DataSheet.co.kr
ICS9370 1
Pin Descriptions
PIN NUMBER
PIN NAME
1, 7, 8, 18, 24, 25,
31, 41, 42, 48
GND
26, 30, 40, 43, 47,
23, 19, 9, 6, 2
CLKC(9:0)
27, 29, 39, 44, 46,
22, 20, 10, 5, 3
CLKT(9:0)
4, 11, 21, 28,
34, 38, 45,
VDD
12 SCLK
13 CLK_INT
14 CLK_INC
15 VDDI2C
16 AVDD
17 AGND
32 FB_OUTC
33 FB_OUTT
35 FB_INT
36 FB_INC
37 SDATA
TYPE
PWR Ground
DESCRIPTION
OUT "Complementary" clocks of differential pair outputs.
OUT "True" Clock of differential pair outputs.
PWR Power supply 2.5V
IN Clock input of I2C input, 5V tolerant input
IN "True" reference clock input
IN "Complementary" reference clock input
PWR 3.3V power for I2C
PWR Analog power supply, 2.5V
PWR
OUT
OUT
IN
IN
IN
Analog ground.
"Complementary" Feedback output, dedicated for external feedback. It
switches at the same frequency as the CLK. This output must be wired
to FB_INC.
"True" " Feedback output, dedicated for external feedback. It switches
at the same frequency as the CLK. This output must be wired to
FB_INT.
"True" Feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error.
"Complementary" Feedback input, provides signal to the internal PLL
for synchronization with CLK_INC to eliminate phase error.
Data input for I2C serial input, 5V tolerant input
0417B—10/29/02
2
Datasheet pdf - http://www.DataSheet4U.net/



Part Number ICS93701
Description DDR Phase Lock Loop Clock Driver
Maker Integrated Circuit Systems
Total Page 9 Pages
PDF Download

ICS93701 Datasheet PDF





Similar Datasheet

1 ICS93701 DDR Phase Lock Loop Clock Driver
Integrated Circuit Systems
2 ICS93705 DDR Phase Lock Loop Zero Delay Clock Buffer
Integrated Circuit Systems





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy