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Integrated Circuit Systems

ICS950208 Datasheet Preview

ICS950208 Datasheet

Programmable Timing Control Hub for P4

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Integrated
Circuit
Systems, Inc.
ICS950208
Programmable Timing Control Hub™ for P4
Recommended Application:
CK-408 clock with driven mode only for Brookdale chipset with
P4 processor.
Output Features:
Pin Configuration
*MULTSEL1/REF1 1
VDDREF 2
X1 3
48 REF0/MULTSEL0*
47 GNDREF
46 VDDCPU
• 3 - Pairs of differential CPU clocks @ 3.3V
• 4 - 3V66 @ 3.3V
• 10 - PCI @ 3.3V
• 1 - 48MHz @ 3.3V fixed
• 1 - 24_48MHz selectable output @ 3.3V
• 2 - REF @ 3.3V, 14.318MHz
Features/Benefits:
• Programmable output frequency.
• Programmable output divider ratios.
• Programmable output rise/fall time.
X2 4
GND 5
*FS2/PCICLK_F0 6
*FS3/PCICLK_F1 7
PCICLK_F2 8
VDDPCI 9
*FS4/PCICLK0 10
PCICLK1 11
PCICLK2 12
GND 13
PCICLK3 14
PCICLK4 15
PCICLK5 16
45 CPUCLKT2
44 CPUCLKC2
43 GNDCPU
42 PD#
41 CPUCLKT0
40 CPUCLKC0
39 VDDCPU
38 CPUCLKT1
37 CPUCLKC1
36 GNDCPU
35 IREF
34 AVDD
33 GND
• Programmable output skew.
• Programmable spread percentage for EMI control.
• Watchdog timer technology to reset system
if system malfunctions.
• Programmable watch dog safe frequency.
• Supports I2C Index read/write and block read/write
operations.
• Uses external 14.318MHz crystal.
Key Specifications:
CPU Output Jitter <150ps
PCICLK6 17
32 VDD3V66
VDDPCI 18
31 3V66_0
Vttpwr_GD# 19
30 3V66_1
RESET# 20
GND 21
29 GND
28 3V66_2
*FS0/48MHz 22
27 3V66_3
*FS1/24_48MHz 23
26 SCLK
AVDD48 24
25 SDATA
48-SSOP
* Internal Pull-Up Resistor of 120K to VDD
Frequency Table
• 3V66 Output Jitter <250ps
• CPU Output Skew <100ps
Bit2 Bit7 Bit6 Bit5 Bit4
FS4 FS3 FS2 FS1 FS0
CPU
MHz
3V66
MHz
0 0 0 0 0 102.00 68.00
PCI
MHz
34.00
0 0 0 0 1 105.00 70.00 35.00
0 0 0 1 0 108.00 72.00 36.00
0 0 0 1 1 111.00 74.00 37.00
0 0 1 0 0 114.00 76.00 38.00
0 0 1 0 1 117.00 78.00 39.00
0 0 1 1 0 120.00 80.00 40.00
0 0 1 1 1 123.00 82.00 41.00
Block Diagram
0 1 0 0 0 126.00 72.00 36.00
0 1 0 0 1 130.00 74.30 37.10
0 1 0 1 0 136.00 68.00 34.00
PLL2
48MHz
0 1 0 1 1 140.00 70.00 35.00
0 1 1 0 0 144.00 72.00 36.00
X1 XTAL
X2 OSC
/2
24_48MHz
REF (1:0)
0 1 1 0 1 148.00 74.00 37.00
0 1 1 1 0 152.00 76.00 38.00
0 1 1 1 1 156.00 78.00 39.00
1 0 0 0 0 160.00 80.00 40.00
1 0 0 0 1 164.00 82.00 41.00
PD#
MULTSEL(1:0)
FS (4:0)
SDATA
SCLK
Vtt_PWRGD#
PLL1
Spread
Spectrum
Control
Logic
Config.
Reg.
CPU
DIVDER
PCI
DIVDER
3V66
DIVDER
3 CPUCLKT (2:0)
3 CPUCLKC (2:0)
PCICLK (6:0), PCICLK_F (1:0)
10
3V66 (3:0)
4
RESET#
I REF
1 0 0 1 0 166.60 66.60 33.30
1 0 0 1 1 170.00 68.00 34.00
1 0 1 0 0 175.00 70.00 35.00
1 0 1 0 1 180.00 72.00 36.00
1 0 1 1 0 185.00 74.00 37.00
1 0 1 1 1 190.00 76.00 38.00
1 1 0 0 0 66.80 66.80 33.40
1 1 0 0 1 100.20 66.80 33.40
1 1 0 1 0 133.60 66.80 33.40
1 1 0 1 1 200.40 66.80 33.40
1 1 1 0 0 66.60 66.60 33.30
1 1 1 0 1 100.00 66.60 33.30
0464B—08/04/03
1 1 1 1 0 200.00 66.60 33.30
1 1 1 1 1 133.33 66.60 33.30




Integrated Circuit Systems

ICS950208 Datasheet Preview

ICS950208 Datasheet

Programmable Timing Control Hub for P4

No Preview Available !

Integrated
Circuit
Systems, Inc.
ICS950208
General Description
The ICS950208 is a single chip clock solution for desktop designs using the Intel Brookdale chipset with PC133 or DDR
memory. It provides all necessary clock signals for such a system.
The ICS950208 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the
first to introduce a whole product line which offers full programmability and flexibility on a single clock device. This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting
under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment. With
all these programmable features ICS's, TCH makes mother board testing, tuning and improvement very simple.
Pin Description
PIN PIN
PIN
#
NAME
TYPE
DESCRIPTION
1
*MULTSEL1/REF1
I/O
3.3V LVTTL input for selection the current multiplier for CPU outputs / 14.318 MHz reference
clock.
2
VDDREF
PWR Ref, XTAL power supply, nominal 3.3V
3 X1 IN Crystal input, Nominally 14.318MHz.
4 X2 OUT Crystal output, Nominally 14.318MHz
5
GND
PWR Ground pin.
6 *FS2/PCICLK_F0 I/O Frequency select latch input pin / 3.3V PCI free running clock output.
7 *FS3/PCICLK_F1 I/O Frequency select latch input pin / 3.3V PCI free running clock output.
8
PCICLK_F2
OUT Free running PCI clock not affected by PCI_STOP# .
9
VDDPCI
PWR Power supply for PCI clocks, nominal 3.3V
10
*FS4/PCICLK0
#N/A #N/A
11
PCICLK1
OUT PCI clock output.
12
PCICLK2
OUT PCI clock output.
13
GND
PWR Ground pin.
14
PCICLK3
OUT PCI clock output.
15
PCICLK4
OUT PCI clock output.
16
PCICLK5
OUT PCI clock output.
17
PCICLK6
OUT PCI clock output.
18
VDDPCI
PWR Power supply for PCI clocks, nominal 3.3V
19 Vttpwr_GD#
IN This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are
valid and are ready to be sampled. This is an active low input.
20
RESET#
OUT
Real time system reset signal for frequency gear ratio change or watchdog timer timeout.
This signal is active low.
21
GND
PWR Ground pin.
22 *FS0/48MHz I/O Frequency select latch input pin / Fixed 48MHz clock output. 3.3V
23 *FS1/24_48MHz I/O Frequency select latch input pin / Fixed 24 or 48MHz clock output. 3.3V.
24
AVDD48
PWR Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
~ This output has 2X drive
0464B—08/04/03
2


Part Number ICS950208
Description Programmable Timing Control Hub for P4
Maker Integrated Circuit Systems
Total Page 19 Pages
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