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Integrated Circuit Systems

ICS9DB202 Datasheet Preview

ICS9DB202 Datasheet

Two 0.7V current mode differential HCSL output pairs

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Integrated
Circuit
Systems, Inc.
ICS9DB202
PCI EXPRESS
JITTER ATTENUATOR
GENERAL DESCRIPTION
The ICS9DB202 is a high perfromance 1-to-2 Dif-
ICS ferential-to-HCSL Jitter Attenuator designed for use
HiPerClockS™ in PCI Express™ systems. In some PCI Express™
systems, such as those found in desktop PCs, the
PCI Express™ clocks are generated from a low
bandwidth, high phase noise PLL frequency synthesizer. In these
systems, a jitter-attenuating device may be necessary in order
to reduce high frequency random and deterministic jitter com-
ponents from the PLL synthesizer and from the system board.
The ICS9DB202 has two PLL bandwidth modes. In low band-
width mode, the PLL loop bandwidth is 500kHz.This setting of-
fers the best jitter attenuation and is still high enough to pass a
triangular input spread spectrum profile. In high bandwidth mode,
the PLL bandwidth is at 1MHz and allows the PLL to pass more
spread spectrum modulation.
For serdes which have x10 reference multipliers instead of x12.5
multipliers, each of the two PCI Express™ outputs (PCIEX0:1)
can be set for 125MHz instead of 100MHz by configuring the
appropriate frequency select pins (FS0:1).
BLOCK DIAGRAM
IREF
+-
Current
Set
nOE0
1 HiZ
0 Enabled
nCLK
CLK
Phase
Detector
Loop
Filter
VCO
÷5
Internal Feedback
Features
Two 0.7V current mode differential HCSL output pairs
1 differential clock input
CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
Maximum output frequency: 140MHz
Output skew: 110ps (maximum)
Cycle-to-cycle jitter: 110ps (maximum)
RMS phase jitter @ 100MHz, (1.5MHz - 22MHz):
2.42ps (typical)
3.3V operating supply
0°C to 70°C ambient operating temperature
Lead-Free package available
Industrial temperature information available upon request
PIN ASSIGNMENT
0
0 ÷4
1 ÷5 1
FS0
0 ÷5
1 ÷4
0
1
PLL_BW 1
2 0 VDDA
CLK 2 19 BYPASS
nCLK 3 18 IREF
FS0 4 17 FS1
VDD 5
16 VDD
GND 6 15 GND
PCIEXT0 7 14 PCIEXT1
PCIEXC0 8 13 PCIEXC1
VDD 9
12 VDD
nOE0 10 11 nOE1
ICS9DB202
20-Lead TSSOP
6.50mm x 4.40mm x 0.92
PCIEXT0
nPCIEXC0
package body
G Package
Top View
ICS9DB202
20-Lead, 209-MIL SSOP
5.30mm x 7.20mm x 1.75mm
body package
F Package
Top View
PCIEXT1
nPCIEXC1
BYPASS
nOE1
1 HiZ
0 Enabled
FS1
9DB202CG
DataSheet4 U .com
www.icst.com/products/hiperclocks.html
1
REV. A OCTOBER 6, 2004




Integrated Circuit Systems

ICS9DB202 Datasheet Preview

ICS9DB202 Datasheet

Two 0.7V current mode differential HCSL output pairs

No Preview Available !

www.DataSheet4U.com
Integrated
Circuit
Systems, Inc.
ICS9DB202
PCI EXPRESS
JITTER ATTENUATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1 PLL_BW Input Pullup Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels.
2 CLK Input Pulldown Non-inverting differential clock input.
3
nCLK
Input
Pullup/
Pulldown
Inverting differential clock input. VDD/2 default when left floating.
4 FS0 Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels.
5, 9, 12, 16
6, 15
7, 8
10, 11
13, 14
VDD
GND
PCIEXT0,
PCIEXC0
nOE0, nOE1
PCIEXC1,
PCIEXT1
Power
Power
Output
Input
Output
Core supply pins.
Power supply ground.
Differential output pairs. HCSL interface levels.
Pulldown
Output enable. When HIGH, forces outputs to HiZ state.
When LOW, enables outputs. LVCMOS/LVTTL interface levels.
Differential output pairs. HCSL interface levels.
17 FS1 Input Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
18
IREF
Input
A fixed precision resistor (475) from this pin to ground provides a
reference current used for differential current-mode PCIEX clock outputs.
19
BYPASS
Power
Pulldown
BYPASS pin. When HIGH. bypass mode, when LOW, PLL mode.
LVCMOS/LVTTL interface levels.
20
VDDA
Power
Analog supply pin. Requires 24series resistor.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C
IN
RPULLUP
RPULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
K
K
TABLE 3A. RATIO OF OUTPUT FREQUENCY TO TABLE 3B. RATIO OF OUTPUT FREQUENCY TO
INPUT FREQUENCY FUNCTION TABLE, FS0
INPUT FREQUENCY FUNCTION TABLE, FS1
Inputs Outputs
Inputs Outputs
FS0 PCIEX0
FS1 PCIEX1
0 5/4
01
11
1 5/4
TABLE 3C. BYPASS TABLE
Inputs
BYPASS
0
1
Mode
PLL Mode
Bypass Mode
(output = inputs)
TABLE 3D. OUTPUT ENABLE
FUNCTION TABLE, NOE0
Inputs Outputs
nOE0
PCIEX0
0 Enabled
1 HiZ
TABLE 3E. OUTPUT ENABLE
FUNCTION TABLE, NOE1
Inputs Outputs
nOE1
PCIEX1
0 Enabled
1 HiZ
TABLE 3F. PLL BANDWIDTH TABLE
Inputs
Bandwidth
PLL_BW
0 500kHz
1 1MHz
9DB202CG
DataSheet4 U .com
www.icst.com/products/hiperclocks.html
2
REV. A OCTOBER 6, 2004



Part Number ICS9DB202
Description Two 0.7V current mode differential HCSL output pairs
Maker Integrated Circuit Systems
Total Page 11 Pages
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