Integrated Circuit Systems ICS9DB104
ICS9DB104 is driven by a differential input pair from a CK409/CK410 main clock generator, such as the ICS952601 or ICS954101. It provides ouputs meeting tight cycle-to-cycle jitter (50ps) and output-to-output skew (50ps) requirements.| Part No. | ICS9DB104 |
|---|---|
| Datasheet | ICS9DB104 Download |
| Manufacturer |  Integrated Circuit Systems |
| Description | Four Output Differential Buffer |
| Buy | Stock & Price |
FEATURES
:● 4 - 0.7V current-mode differential output pairs
● Supports zero delay buffer mode and fanout mode
● Bandwidth programming available Key Specifications:
● Outputs cycle-cycle jitter: < 50ps
● Outputs skew: < 50ps
● +/- 300ppm frequency accuracy on output clocks
FEATURES
/Benefits:● Supports tight ppm accuracy clocks for Serial-ATA
● Spread spectrum modulation tolerant, 0 to -0.5% down spread and +/- 0.25% center spread
● Supports undriven differential output pair in PD# and SRC_STOP# for power management. Pin Configuration VDD SRC_IN SRC_IN# GND VDD DIF_1 DIF_1# OE_1 DIF_2 DIF_2# VDD BYPASS#/PLL SCLK SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDDA GNDA IREF GND VDD DIF_6 DIF_6# OE_6 DIF_5 DIF_5# VDD HIGH_BW# SRC_STOP# PD# 28-pin SSOP & TSSOP 0767C—07/19/04 DataSheet 4 U .com ICS9DB104 Integrated Circuit Systems, Inc. ICS9DB104 Pin
DESCRIPTION
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PIN NAME VDD SR...
