Integrated Circuit Systems ICS9DB102
The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC output pair from an ICS CK409/CK410-compliant main clock generator such as the ICS952601 or ICS954101. It attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without Spread-Spectrum clocking.| Part No. | ICS9DB102 |
|---|---|
| Datasheet | ICS9DB102 Download |
| Manufacturer |  Integrated Circuit Systems |
| Description | 2 Output PCI Express Buffer |
| Buy | Stock & Price |
FEATURES
:● 2 - 0.7V current mode differential output pairs (HSCL) Key Specifications:
● Cycle-to-cycle jitter < 35ps
● Output-to-output skew < 25 ps
FEATURES
/Benefits:● CLKREQ# pin for outputs 1 and 4/output enable for Express Card applications
● PLL or bypass mode/PLL can dejitter incoming clock
● Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL’s
● Spread Spectrum Compatible/tracks spreading input clock for low EMI
● SMBus Interface/unused outputs can be disabled Pin Configuration PLL_BW CLK_INT CLK_INC **CLKREQ0# VDD GND PCIEXT0 PCIEXC0 VDD SMBDAT 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDDA GNDA IREF **CLKREQ1# VDD GND PCIEXT1 PCIEXC1 VDD SMBCLK Note: Pins preceeded by '**' have internal 120K ohm pull down resistors 20-pin SSOP & TSSOP 0852BC—09/12/05 *Other names and brands may be claimed as the property of others. DataSheet 4 U .com ICS9DB102 Integrated Circuit Systems, Inc. ICS9DB102 Pin
DESCRIPTION
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17...
