ICS9DB102 Datasheet and Specifications PDF

The ICS9DB102 is a Two Output Differential Buffer.

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Part NumberICS9DB102 Datasheet
ManufacturerIDT
Overview The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC output pair from an ICS CK410/CK505-compliant main clock. It attenuates jitter.
* 2 - 0.7V current mode differential output pairs (HCSL) Features/Benefits
* CLKREQ# pin for outputs 1 and 4/output enable for Express Card applications
* PLL or bypass mode/PLL can dejitter incoming clock
* Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL’s
* Spread Spectrum Com.
Part NumberICS9DB102 Datasheet
Description2 Output PCI Express Buffer
ManufacturerIntegrated Circuit Systems
Overview PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PLL_BW CLK_INT CLK_INC **CLKREQ0# VDD GND PCIEXT0 PCIEXC0 VDD SMBDAT SMBCLK VDD PCIEXC1 PCIEXT1 GND VDD **CLKREQ1# PIN NAME PIN TYPE IN IN IN IN PWR PWR.
* 2 - 0.7V current mode differential output pairs (HSCL) Key Specifications:
* Cycle-to-cycle jitter < 35ps
* Output-to-output skew < 25 ps Features/Benefits:
* CLKREQ# pin for outputs 1 and 4/output enable for Express Card applications
* PLL or bypass mode/PLL can dejitter incoming clock
* Selecta.
Part NumberICS9DB102 Datasheet
DescriptionTwo Output Differential Buffer
ManufacturerRenesas
Overview The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC output pair from an ICS CK410/CK505-compliant main clock. It attenuates jitter.
* 2 - 0.7V current mode differential output pairs (HCSL) Features/Benefits
* CLKREQ# pin for outputs 1 and 4/output enable for Express Card applications
* PLL or bypass mode/PLL can dejitter incoming clock
* Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL’s
* Spread Spectrum Com.