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Integrated Circuit Systems

ICS9FG1904B-1 Datasheet Preview

ICS9FG1904B-1 Datasheet

Frequency Generator

No Preview Available !

Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
Frequency Generator for CPU, PCIe Gen 1, PCIe Gen 2 & FBD
Recommended Application:
DB1900GS/GSO with 15:4 output grouping
Features:
• Power up default is all outputs in 1:1 mode
• DIF_(14:0) can be “gear-shifted” from the input CPU
Host Clock
• DIF_(18:15) can be “gear-shifted” from the input CPU
Host Clock
• Spread spectrum compatible
• Supports output clock frequencies up to 400 MHz
• 8 Selectable SMBus addresses
• SMBus address determines PLL or Bypass mode
Key Specifications:
• DIF output cycle-to-cycle jitter < 50ps
• DIF output-to-output skew < 100ps within a group
Functionality at Power Up (PLL Mode)
FS_A_4101
1
0
CLK_IN (CPU FSB)
MHz
100 <= CLK_IN < 200
200<= CLK_IN <= 400
DIF_(18:0)
MHz
CLK_IN
CLK_IN
1. FS_A_410 is a low-threshold input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for
correct values.
Power Down Functionality
INPUTS
CKPWRGD/ CLK_IN/
PD#
CLK_IN#
1 Running
0X
OUTPUTS
DIF/DIF#
Running
Hi-Z
PLL State
ON
OFF
Pin Configuration
IREF
GNDA
VDDA
HIGH_BW#
FS_A_410
DIF_0
DIF_0#
DIF_1
DIF_1#
GND
VDD
DIF_2
DIF_2#
DIF_3
DIF_3#
DIF_4
DIF_4#
OE_01234#
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
1
2
3
4
5
6
7
8
9
10
ICS9FG1904-1
11
12
13
14
15
16
17
18
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
54 OE14#
53 DIF_13#
52 DIF_13
51 OE13#
50 DIF_12#
49 DIF_12
48 OE12#
47 VDD
46 GND
45 DIF_11#
44 DIF_11
43 OE11#
42 DIF_10#
41 DIF_10
40 OE10#
39 DIF_9#
38 DIF_9
37 OE9#
1255B—08/03/07
72-pin MLF
Other names and brands may be claimed as the property of others.




Integrated Circuit Systems

ICS9FG1904B-1 Datasheet Preview

ICS9FG1904B-1 Datasheet

Frequency Generator

No Preview Available !

Integrated
Circuit
Systems, Inc.
ICS9FG1904B-1
Pin Description
PIN #
PIN NAME
1 IREF
2 GNDA
3 VDDA
4 HIGH_BW#
5 FS_A_410
6 DIF_0
7 DIF_0#
8 DIF_1
9 DIF_1#
10 GND
11 VDD
12 DIF_2
13 DIF_2#
14 DIF_3
15 DIF_3#
16 DIF_4
17 DIF_4#
18 OE_01234#
19 SMBCLK
20 SMBDAT
21 OE5#
22 DIF_5
23 DIF_5#
24 OE6#
25 DIF_6
26 DIF_6#
27 VDD
28 GND
29 OE7#
30 DIF_7
31 DIF_7#
32 OE8#
33 DIF_8
34 DIF_8#
35 SMB_A0
36 SMB_A1
PIN TYPE
DESCRIPTION
This pin establishes the reference current for the differential current-mode
OUT output pairs. This pin requires a fixed precision resistor tied to ground in order
to establish the appropriate current. 475 ohms is the standard value.
PWR Ground pin for the PLL core.
PWR 3.3V power for the PLL core.
IN 3.3V input for selecting PLL Band Width
0 = High, 1= Low
3.3V tolerant low threshold input for CPU frequency selection. This pin
IN requires CK410 FSA. Refer to input electrical characteristics for Vil_FS and
Vih_FS threshold values.
OUT 0.7V differential true clock output
OUT 0.7V differential complement clock output
OUT 0.7V differential true clock output
OUT 0.7V differential complement clock output
PWR Ground pin.
PWR Power supply, nominal 3.3V
OUT 0.7V differential true clock output
OUT 0.7V differential complement clock output
OUT 0.7V differential true clock output
OUT 0.7V differential complement clock output
OUT 0.7V differential true clock output
OUT 0.7V differential complement clock output
IN
Active low input for enabling DIF pairs 0, 1, 2, 3 and 4.
1 = tri-state outputs, 0 = enable outputs
IN Clock pin of SMBUS circuitry, 5V tolerant
I/O Data pin of SMBUS circuitry, 5V tolerant
IN Active low input for enabling DIF pair 5.
1 = tri-state outputs, 0 = enable outputs
OUT 0.7V differential true clock output
OUT 0.7V differential complement clock output
IN Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
OUT 0.7V differential true clock output
OUT 0.7V differential complement clock output
PWR Power supply, nominal 3.3V
PWR Ground pin.
IN
Active low input for enabling DIF pair 7.
1 = tri-state outputs, 0 = enable outputs
OUT 0.7V differential true clock output
OUT 0.7V differential complement clock output
IN Active low input for enabling DIF pair 8.
1 = tri-state outputs, 0 = enable outputs
OUT 0.7V differential true clock output
OUT 0.7V differential complement clock output
IN SMBus address bit 0 (LSB)
IN SMBus address bit 1
1255B—08/03/07
2



Part Number ICS9FG1904B-1
Description Frequency Generator
Maker Integrated Circuit Systems
Total Page 22 Pages
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