ICS9FG1904B-1
Features
:
- Power up default is all outputs in 1:1 mode
- DIF_(14:0) can be “gear-shifted” from the input CPU
Host Clock
- DIF_(18:15) can be “gear-shifted” from the input CPU
Host Clock
- Spread spectrum patible
- Supports output clock frequencies up to 400 MHz
- 8 Selectable SMBus addresses
- SMBus address determines PLL or Bypass mode
Key Specifications:
- DIF output cycle-to-cycle jitter < 50ps
- DIF output-to-output skew < 100ps within a group
Functionality at Power Up (PLL Mode)
FS_A_4101
1 0
CLK_IN (CPU FSB) MHz
100 <= CLK_IN < 200 200<= CLK_IN <= 400
DIF_(18:0) MHz
CLK_IN CLK_IN
1. FS_A_410 is a low-threshold input. Please see the VIL_FS and VIH_FS specifications in the Input/Supply/mon Output Parameters Table for correct values.
Power Down Functionality
INPUTS
CKPWRGD/...
